From Microvias to Fine-Pitch Fanout: Designing HDI PCBs with CAD Confidence

High-density interconnect HDI PCB design is a different discipline from conventional multilayer board layout. It demands tighter rules, laser-drilled microvias, sequential lamination awareness, and a CAD workflow that keeps manufacturability at the center of every decision. The following sections cover stackup definition, microvia planning, escape routing, and design validation inside modern PCB CAD software. For a detailed companion walkthrough, see How to Design for HDI PCB Using CAD Software.

Setting Up HDI-Specific CAD Rules and Constraints

The first step in designing an HDI board inside CAD software is to stop treating it like a standard multilayer PCB. High-density interconnect designs require a different constraint philosophy because they rely on microvias, sequential lamination, and much finer conductor geometries. In the CAD layer stack manager, define the full build-up, including core, prepreg, copper foil, and the dielectric layers that will be laser-drilled. Many CAD tools allow sub-stack regions for each lamination cycle. This matters because a microvia that spans two layers in a 1+N+1 build-up is not the same as a buried via that spans the core. If the CAD stackup does not reflect the actual sequential lamination sequence, the design rule checker cannot correctly identify illegal via spans or drill pairs.

Once the stackup is defined, move to the constraint manager and create HDI-specific rules. Typical fine-line rules for HDI boards include 75 µm trace/space or 50 µm trace/space for dense areas, annular ring requirements of 75–100 µm on laser vias, and microvia diameters of 75–100 µm. Set via span rules so that blind microvias only connect adjacent layers in the build-up, while buried vias are limited to their intended core or sub-laminate ranges. Use pad and via classes to separate via types, and define via-in-pad rules for BGA escape areas. CAD constraint systems should also check microvia aspect ratio, typically 1:1 or 1:1.5 depending on the fabricator’s laser drilling capability. Adding DFM values from a manufacturing partner at this stage prevents costly redesign later.

Electrical constraints are equally important. In HDI boards for automotive, medical, and high-speed telecom applications, differential pairs often require 100 Ω impedance while single-ended nets require 50 Ω. Set up net classes, differential pair profiles, and length-matching tolerances before routing begins. If the stackup includes low-loss or high-frequency materials, update the material library with the correct dielectric constant and loss tangent so the CAD impedance calculator produces accurate values. This rules-first approach makes routing and validation far more predictable.

Stackup Planning, Microvia Strategies, and Fanout Routing in CAD

HDI stackup planning begins with the number of build-up layers. A 1+N+1 stackup places one microvia layer on the top and bottom of a conventional N-layer core, while a 2+N+2 stackup adds two sequential lamination layers on each side. In CAD, this architecture should be represented as separate layer pairs, not simply as additional layers in a standard through-hole stackup. The microvia strategy determines whether vias are stacked or staggered. Stacked microvias save space and provide lower inductance, but they require filled via plating and tighter manufacturing control. Staggered microvias are often more reliable in high-layer-count or high-reliability designs, but they consume more routing space. The CAD tool should use via span definitions to prevent accidental layer-to-layer connections that violate the intended architecture.

For fine-pitch BGA and chip-scale packages, via-in-pad is usually the only practical escape method. A 0.4 mm pitch BGA leaves very little space for a traditional dog-bone via pattern. In CAD, place microvias directly inside the SMD pad and assign them to the appropriate blind via span from the outer layer to the next inner layer. Use the fanout engine with HDI constraints enabled. The tool should generate a matrix of microvias, but the pattern must be tuned for solder mask opening, paste mask, and fill requirements. Some CAD systems apply teardrops or tapered entries automatically to improve manufacturability. When routing differential pairs away from the fanout, keep the pair coupled through the escape region and avoid routing one side of a pair around a via that creates excessive length mismatch.

Layer assignment is another critical CAD decision. Sensitive high-speed signals should be routed on inner layers immediately adjacent to a solid reference plane. For an HDI board with a large processor or FPGA, the top and bottom microvia layers are mainly used for component fanout, while the core layers carry longer high-speed routes and power distribution. In a rigid-flex HDI design, keep sequential lamination transitions away from bend areas and use the CAD bending tool to verify copper stress near blind via boundaries. A clean stackup with clearly defined laser drill layer pairs and via span limits reduces the risk of creating vias that cannot be fabricated.

DRC Validation, Signal Integrity, and DFM for HDI CAD Outputs

After routing, the CAD design rule check must do more than find spacing violations. HDI-specific DRC should examine microvia capture pad size, via-to-trace clearance, drill-to-copper distance, soldermask clearance around via-in-pad structures, and paste mask openings. Stacked microvias need a rule that checks for filled via plating requirements and avoids placing a stacked via on an outer copper feature that cannot support plating. Staggered microvias require additional checks for land-to-land spacing and potential resin recession. Define a dedicated DRC matrix for the outer build-up layers and use the CAD tool’s net class and area rule features to apply tighter checks only where needed. This is far more efficient than assigning the same strict rules across the entire board.

Signal and power integrity simulation should be part of the HDI CAD flow. Microvias have different electrical characteristics than through-hole vias, and their shorter stubs often improve high-speed performance, but the transition from pad to microvia still creates an impedance discontinuity. Use the CAD tool’s integrated or linked SI tools to extract S-parameters for critical nets and verify that the impedance profile stays within tolerance. For power integrity, analyze plane resonance and decoupling placement around high-current BGA rails. HDI boards can pack many power domains into a small area, so place decoupling capacitors on the secondary side with short microvia paths to the power and ground planes. Via-in-pad routing reduces loop inductance, but it also requires filled and capped vias; make sure the CAD output clearly identifies these features.

Finally, generate fabrication and assembly outputs that match the intended HDI manufacturing flow. Use Gerber X2, ODB++, or IPC-2581 output with separate mechanical drill files and laser drill files. Include a detailed stackup drawing, material callouts, impedance table, surface finish, via fill requirements, and any backdrill notes. Run a DFM check against the fabricator’s HDI capabilities, especially for laser via diameter, aspect ratio, annular ring, and minimum dielectric thickness. A practical example is a 0.4 mm pitch processor board where properly configured CAD constraints, via-in-pad fanout, and laser microvias reduced the layer count from 12 to 8 while still passing signal integrity verification. That outcome depends on treating DRC, SI, and DFM as a single continuous loop rather than separate end-of-project tasks.

Kofi Mensah

Accra-born cultural anthropologist touring the African tech-startup scene. Kofi melds folklore, coding bootcamp reports, and premier-league match analysis into endlessly scrollable prose. Weekend pursuits: brewing Ghanaian cold brew and learning the kora.